d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct564 octal d-type flip-flop; positive-edge trigger; 3-state; inverting for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation octal d-type ?ip-?op; positive-edge trigger; 3-state; inverting 74hc/hct564 features 3-state inverting outputs for bus oriented applications 8-bit positive-edge triggered register common 3-state output enable input independent register and 3-state buffer operation output capability: bus driver i cc category: msi general description the 74hc/hct564 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct564 are octal d-type flip-flops featuring separate d-type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. a clock (cp) and an output enable (oe) input are common to all flip-flops. the 8 flip-flops will store the state of their individual d-inputs that meet the set-up and hold times requirements on the low-to-high cp transition. when oe is low, the contents of the 8 flip-flops are available at the outputs. when oe is high, the outputs go to the high impedance off-state. operation of the oe input does not affect the state of the flip-flops. the 564 is functionally identical to the 574 but has inverting outputs. the 564 is functionally identical to the 534, but has a different pinning. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc ; for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl/ t plh propagation delay cp to q n c l = 15 pf; v cc =5 v 15 16 ns f max maximum clock frequency 127 62 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per flip-flop notes 1 and 2 27 27 pf
december 1990 3 philips semiconductors product speci?cation octal d-type ?ip-?op; positive-edge trigger; 3-state; inverting 74hc/hct564 pin description pin no. symbol name and function 1 oe 3-state output enable input (active low) 2, 3, 4, 5, 6, 7, 8, 9 d 0 to d 7 data inputs 10 gnd ground (0 v) 11 cp clock input (low-to-high, edge-triggered) 19, 18, 17, 16, 15, 14, 13, 12 q 0 to q 7 3-state ?ip-?op outputs 20 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation octal d-type ?ip-?op; positive-edge trigger; 3-state; inverting 74hc/hct564 fig.4 functional diagram. function table notes 1. h = high voltage level h = high voltage level one set-up time prior to the low-to-high cp transition l = low voltage level l = low voltage level one set-up time prior to the low-to-high cp transition z = high impedance off-state - = low-to-high clock transition operating modes inputs internal flip-flops outputs oe cp d n q 0 to q 7 load and read register l l - - l h l h h l load register and disable outputs h h - - l h l h z z fig.5 logic diagram.
december 1990 5 philips semiconductors product speci?cation octal d-type ?ip-?op; positive-edge trigger; 3-state; inverting 74hc/hct564 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 50 18 14 165 33 28 205 41 35 250 50 43 ns 2.0 4.5 6.0 fig.6 t pzh / t pzl 3-state output enable time oe to q n 44 16 13 140 28 24 175 35 30 210 42 36 ns 2.0 4.5 6.0 fig.8 t phz / t plz 3-state output disable time oe to q n 50 18 14 135 27 23 170 34 29 205 41 35 ns 2.0 4.5 6.0 fig.8 t thl / t tlh output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.6 t w clock pulse width high or low 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.6 t su set-up time d n to cp 60 12 10 6 2 2 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.7 t h hold time d n to cp 5 5 5 0 0 0 5 5 5 5 5 5 ns 2.0 4.5 6.0 fig.7 f max maximum clock pulse frequency 6.0 30 35 38 115 137 4.8 24 28 4.0 20 24 mhz 2.0 4.5 6.0 fig.6
december 1990 6 philips semiconductors product speci?cation octal d-type ?ip-?op; positive-edge trigger; 3-state; inverting 74hc/hct564 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf input unit load coefficient oe d 0 to d 7 cp 0.80 0.25 1.00 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 19 35 44 53 ns 4.5 fig.6 t pzh / t pzl 3-state output enable time oe to q n 19 35 44 53 ns 4.5 fig.8 t phz / t plz 3-state output disable time oe to q n 19 30 38 45 ns 4.5 fig.8 t thl / t tlh output transition time 5 12 15 18 ns 4.5 fig.6 t w clock pulse width high or low 18 8 23 27 ns 4.5 fig.6 t su set-up time d n to cp 12 3 15 18 ns 4.5 fig.7 t h hold time d n to cp 3 - 2 3 3 ns 4.5 fig.7 f max maximum clock pulse frequency 27 56 22 18 mhz 4.5 fig.6
december 1990 7 philips semiconductors product speci?cation octal d-type ?ip-?op; positive-edge trigger; 3-state; inverting 74hc/hct564 ac waveforms fig.6 waveforms showing the clock (cp) to output ( q n ) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.7 waveforms showing the data set-up and hold times for the data input (d n ). the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.8 waveforms showing the 3-state enable and disable times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. package outlines see 74hc/hct/hcu/hcmos logic package outlines .
|
